High efficiency semiconductor chips are possible due to large concentrations of circuit elements on a single chip. However, as the number of circuit elements on a chip increase, so also increases the probability that a circuit element will fail rendering the total chip unusable. To prevent such a loss, additional circuit elements have been designed into the chips. Defective circuit elements are identified and then disconnected, and selected additional spare elements are connected to produce a working chip. This ability to use additional circuit elements to reconfigure a circuit design produces a higher yield in semiconductor production. In addition, the ability to selectively disconnect or connect circuit elements on a chip or wafer can be used to provide customization wherein the reconfiguration of the circuit is employed to modify the function of the circuit.
Additionally, in wafer scale integration, a number of selectable integrated circuit devices are fabricated on a wafer. In general, the devices need not all be of the same type. After testing, the appropriate functional devices are electrically connected together to make the overall circuit on the wafer. Both redundancy and customization may be involved in the selection of devices and their connections. The ability to make electrical connections is a great advantage over the ability to break connections since this allows testing of the individual integrated circuit devices.
In order to remove a defective or undesired circuit element from the good or desired circuit elements, an existing conductive link joining the defective circuit element to the good circuit elements can be restructured to produce an electrically non-conductive link. The most common restructurable conductive path technique for integrated circuits is to destroy the existing link. In destructive techniques, the link (fuse) can be melted by directing a very large current through the link, or it may be vaporized by a powerful energy beam. Both the melting and vaporizing approaches produce a gap in the link which renders the link electrically nonconductive. The gap is created as a result of the high energy applied to the link which produces a movement or transport of conductive material out of the link.
Methods for activation of a spare circuit element or "writing of a conductive link" can also involve the bulk transport of conductive material. These activation methods are "mass additive" as opposed to "mass substrative" in that material is added in to form an electrically conductive link rather than subtracted out to destroy an electrically conductive link. Such methods are described by J. Raffel, M. Naiman, R. Burke, G. Chapman, and P. Gottschalk, "Laser Programmed Vias For Restructurable VLSI," International Electron Device Meeting (IEDM), pp. 132-135 (1980); and J. Yasaitis, G. Chapmen, and J. Raffel,"Low Resistance Laser Formed Lateral Links," IEEE Electron Device Letters, EDL-3, pp. 184-186 (1982).
Both the mass additive and mass subtractive techniques have several disadvantages. One disadvantage is that whenever there is forced movement of material, some portions of that material will splatter onto other areas of the chip. The splattered material can produce flaws in other circuit elements. A further disadvantage of these methods is that they require a high energy input which will destroy any passivation layer over the link and which is capable of inflicting thermal damage to surrounding circuits. As a result, these methods impose design rules which limit how close circuit elements can be placed to each other, and therefore are not beneficial in very high density semiconductor chips.
Other methods which do not require the material movement associated with mass additive and mass subtractive techniques are also known. One of these techniques requires a region of undoped polycrystalline material to serve as a link positioned between two retions of heavily doped polycrystalline material. The link of undoped material is essentially electrically nonconductive. However, a laser beam provides an energy source to activate dopant atoms from the neighboring heavily doped semiconductor regions causing them to diffuse into the undoped link. The diffused dopant atoms turn the link into an electrically conductive path joining the two heavily doped regions. This technique is described in articles by: O. Minato, T., Masuhara, T. Sasaki, Y. Sakai, and K. Yashizaki, "A High-Speed Hi-CMOS II 4K Statis RAM," IEEE J. Solid-State Circuits, SC-16, pp. 449-453 (1981); and M. Hongo, T. Miyauchi, H. Yamaguchi, T. Masuhara, and O. Minato, "Connecting Conductors On Semiconducting Devices by Lasers," Conference on Lasers and Electro-Optics, IEEE, p. 62 (1982).
While this technique does produce an electrically conductive link, the link still has an undesirably high resistance of 500 or more ohms. But an even greater disadvantage of this technique is the requirement that the undoped polycrystalline region remain undoped during the manufacturing process of the chip. This requires additional masking steps to protect the undoped region and prevents the use of economical doping techniques such as thermal diffusion or blanket ion implantation methods.
Another technique of laser activation of conductive links between circuit elements is described in U.S. Pat. No. 4,462,150 to Nishimura et al. issued July 31, 1984 for "Method of Forming Energy Beam Activated Conductive Regions between Circuit Elements;" and by D. L. Parker, F. Lin, and D. Zhang, "Laser Polysilicon Link Making," IEEE Trans. on Components, Hybrids, and Manufacturing Technology, CHMT-7, pp. 438-442 (1984). This technique requires the formation of an undoped region of polycrystalline material between two doped regions of polycrystalline material. Then dopant atoms are implanted in the undoped portion and left unannealed. A laser beam can then be directed at the link region to provide the energy to anneal the region to produce a conductive link. This technique does produce links of low resistance, but to achieve a low resistance, dopant atoms must be provided in doses of 5.times.10.sup.15 atoms/cm.sup.2 or more. Further, this technique still requires the creation of an initial undoped region of polycrystalline material which necessitates more complicated doping techniques including an additional masking step.
Accordingly, a general object of the present invention is to provide a method of reconfiguring conductive paths for integrated circuits without the material splatter and circuit damage problems associated with the high power intensities of prior art techniques while avoiding the process complications associated with the use of undoped, intrinsic link regions.
An additional object is to eliminate the need of maintaining an undoped intrinsic region of polycrystalline material.
A further object is to utilize a relatively low ion implant dose to create a nonconducting link.
Yet another object is to enable restructuring of circuit element connections without destruction of the passivation dielectric layer.